1. Field of the Invention
The present invention generally relates to modulator/demodulator systems (i.e. modems), and more particularly to a self-clocking demodulator for recovering phase encoded digital data.
2. Description of the Prior Art
Modem systems commonly used today transmit digital data by phase encoding the digital data on an analogue carrier signal. The digital data rate may vary and the modulator and demodulator must be simultaneously configured for a selected data rate. Our invention uses a phase locked loop to lock onto a received stream of data bits whose rate can vary over a wide range. The following patents disclose phase lock loop systems which are illustrative of the prior art.
U.S. Pat. No. 4,375,693 to Kuhn discloses an adaptive sweep bit synchronizer capable of acquisition and operation over an arbitrarily broad range of data rates.
U.S. Pat. No. 4,855,683 to Troudet et al., discloses digital phase locked loop circuit with bounded jitter. FIG. 2 shows a controller 217 increasing the frequency of a VCO 201 in response to signals from a frequency window comparator 208.
U.S. Pat. No. 4,816,774 to Martin shows a frequency synthesizer with compensation. FIG. 1 shows the PLL has a programmable divider 16 for varying values to the divider for fractional division to produce a desired output frequency.
U.S. Pat. No. 4,668,922 to Crawford et al., shows a fast phase lock frequency synthesizer. FIG. 1 shows the use of a divide by N control.
U.S. Pat. No. 4,654,859 to Kung et al., discloses a frequency synthesizer for a frequency hopping communication system. FIG. 1 shows a microprocessor controller connected to a programmable divider of the PLL.
U.S. Pat. No. 4,636,747 to Selim discloses a system and method for wideband, continuous tuning of an oscillator. The oscillator is continuously tuned over its entire operating range by controlling a resolver in the feedback loop around the oscillator.
The Japanese patent abstract to Kanzaki, No. JAO221714, shows a discriminator 5 detecting an input signal A and an output signal B of the VCO 3. A synchronizing frequency detector 6, a correction voltage generating circuit, and a voltage adder circuit 8 are used to make the output frequency coincident with the reception frequency. Japanese patent abstract to Mori, No. JAO121318, shows reset timing generation circuit connected to the divider 12 of the phase locked loop.
U.S Pat. No. 4,748,425 to Heck shows a VCO range shift and modulation device for use with a PLL frequency synthesizer VCO.
U.S. Pat. No. 4,689,581 to Talbot shows an integrated circuit PLL timing apparatus. FIG. 1 shows the PLL connected with a microcomputer on a single chip.
U.S. Patent to Turney discloses a phase locked loop with an out of lock detector control of the loop filter and divider. In this patent, the control unit 26 does not sense the VCO control voltage. The frequency of the reference source (the frequency which is input to phase locked loop) is fixed.
U.S. Pat. No. 4,654,859 to Kung discloses a frequency synthesizer for a frequency hopping communication system. In this patent, a microprocessor controller is provided which changes the count N in the feedback divider circuit. However, the microprocessor controller 34 merely changes the divide count N in some predetermined sequence so that data can be transmitted in a "frequency-hopping" fashion.